Design of Wideband Continuous-Time ΔΣ ADCs Using Two-Step Quantizers
نویسندگان
چکیده
Continuous-time delta sigma (CT-4Σ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of 4Σ ADCs. We proposed using two-step quantizer in a single-loop CT-4Σ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4order continuous-time delta sigma modulator (CT4ΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-4ΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.
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